The present invention relates to solid-state imagers and, particularly to an amplifying type solid-state imager of a capacitor load operation system and a method of driving the same.
As demand for enhancing resolution of a solid-state imager increases, internal amplifying type solid-state imaging devices for amplifying a charge of an optical signal at every pixel have been developed. As typical examples of the internal amplifying type solid-state imaging device, there are various kinds of imaging device structures, such as a static induced transistor (SIT), an amplifying type MOS (metal oxide semiconductor) imager (AMI), a charge modulation device (CMD) and BASIS (base-stored image sensor) using bipolar transistors as pixels.
One of such amplifying type solid-state imaging devices will be described below. In this amplifying type solid-state imaging device, holes (signal charges) generated by photoelectric conversion are accumulated in a p-type potential well of an n-channel MOS transistor (pixel MOS transistor) and the change of a channel current based on a potential fluctuation in the p-type potential well (i.e., change of potential in the back gate) is output as a pixel signal.
FIG. 1 of the accompanying drawings shows an example of the amplifying type solid-state imaging device.
As shown in FIG. 1, an amplifying type solid-state imaging device 12 a plurality of pixel MOS transistors (unit pixels (cells)) 1 arrayed in a matrix fashion. The gate of each pixel MOS transistor 1 is connected to a vertical scanning line 3 selected by a vertical scanning circuit 2 composed of a shift register or the like, the drain thereof is connected to a power supply V.sub.DD and the source thereof is connected to a vertical signal line 5. A load MOS transistor 6 whose gate is applied with a bias voltage V.sub.B is connected between each vertical signal line 5 and the ground. A sample and hold circuit 7 for sampling and holding a pixel signal is connected to the vertical signal line 5. In FIG. 1, reference numeral 8 depicts a horizontal scanning circuit composed of a shift register or the like. The horizontal scanning circuit 8 sequentially supplies horizontal scanning pulses .phi.H (.phi.H.sub.1, . . . .phi.H.sub.n, .phi.H.sub.n+1, . . .) to the gate of a horizontal MOS switch 9 to thereby output the pixel signal supplied thereto from the sample and hold circuit 7 to the outside through a horizontal signal line 10.
In the amplifying type solid-state imaging device 12, the unit pixel, i.e., the pixel MOS transistor 1 is selected by the vertical scanning circuit 2 through the vertical scanning line 3. Then, a signal generated from a source-follower circuit composed of the pixel MOS transistor 1 and a load MOS transistor 6 connected to the vertical signal line 5 as a constant current source is sampled and held by the sample and hold circuit 7 in response to a sample and hold pulse .phi.SH and the horizontal MOS switches 9 connected to the horizontal scanning circuit 8 are sequentially turned on, thereby a signal of each pixel MOS transistor 1 being output through the horizontal signal line 10.
Specifically, the selected pixel MOS transistor 1 is operated in a source-follower fashion by the load MOS transistor 6 to output the source potential through the sample and hold circuit 7 and the horizontal MOS switch 9 under the condition that a current is constantly flowed to the pixel MOS transistor 1. When this operation is carried out at every horizontal scanning line while the vertical scanning line 3 for scanning the pixel MOS transistor 1 is being changed, there can be obtained the signal output of the solid-state imaging device.
However, in the above-mentioned case, operation conditions of the pixel MOS transistor 1 disposed away from the load MOS transistor 6 and the pixel MOS transistor 1 disposed near the load MOS transistor 6 are changed by a distributed resistance with the result that sensitivity is deteriorated in the vertical direction.
If a constant current property of the load MOS transistor 6 operated as the constant current source is unsatisfactory, there is then the disadvantage that sensitivity of the solid-state imaging device is lowered. In other words, the load MOS transistor 6 operated as the constant current source is not always an ideal constant current source. Therefore, if the source current of the pixel MOS transistor 1 is changed, then the constant current also is fluctuated very slightly and a fluctuated amount of the constant current causes sensitivity to be lowered.
Moreover, since the constant current is always flowed when a signal voltage is read out from the pixel MOS transistor 1, an imaging device consumes much power.
Further, when the constant current of the load MOS transistor 6 is fluctuated, there is generated a vertical stripe-shaped fixed pattern noise (FPN) which is difficult to be eliminated by signal processing.
As a signal read circuit of an image sensor using a photoelectric conversion element of a photodiode, there is proposed a signal read circuit in which a feedback portion of a preamplifier of the signal read circuit is composed of a parallel circuit of a capacitor element and a reset switching element (see Japanese laid-open patent publication No. 61-49562). In this signal read circuit, a read transistor is turned on and off by a scanning pulse supplied from a scanning circuit during a period in which a reset switching element is set in it off-state.
The same assignee of the present application has previously proposed an amplifying type solid-state imaging device of a capacitor load operation system in which sensitivity can be made uniform, sensitivity can be increased and a power consumption can be reduced.
FIG. 2 shows an example of an amplifying type solid-state imaging device of a capacitor load operation system.
As shown in FIG. 2, an amplifying type solid-state imaging device 28 includes a plurality of light receiving elements composing unit pixels (cells), e.g., pixel transistors, i.e., pixel MOS transistors 1 in this embodiment arrayed in a matrix fashion. The gate of pixel MOS transistor 1 of each row is connected to a vertical scanning line 3 selected by a vertical scanning circuit 2 composed of a shift register or the like, the drain thereof is connected to a power supply V.sub.DD and the source thereof at every column is connected to a vertical signal line 5.
A load capacitor element (load capacitor) 24 for holding a signal voltage (electric charge) is connected to the vertical signal line 5 through an operation MOS switch 23, i.e., the load capacitor element 24 is connected between the vertical signal line 5 and a first potential, i.e., the ground potential in this embodiment. An operation pulse .phi..sub.RD is applied to the gate of the operation MOS switch 23.
A load capacitor reset MOS switch 25 is parallelly connected to the load capacitor element 24 and a reset pulse .phi..sub.RST is applied to the gate of the load capacitor reset MOS switch 25.
In FIG. 2, reference numeral 8 depicts a horizontal scanning circuit composed of a shift register or the like. This horizontal scanning circuit 8 sequentially supplies horizontal scanning pulses .phi.H (.phi.H.sub.1, . . . .phi.H.sub.n, .phi.H.sub.n+1, . . .) to the gate of the horizontal MOS switch 9 connected to the horizontal signal line 10. An output resistor 26 and a bias power supply 27 are connected between an output side of the horizontal signal line 10 and the ground.
In the amplifying type solid-state imaging device 28, during a horizontal blanking period in which a signal charge is read out from the pixel MOS transistor 1, vertical scanning signals (i.e., vertical selection pulses) .phi.V (.phi.V.sub.1, . . . .phi.V.sub.i, .phi.V.sub.i+1, . . .) from the vertical scanning circuit 2 are sequentially applied to the vertical scanning line 3 of each row to thereby sequentially select the pixel MOS transistor 1 of each row. Also, the operation MOS switch 23 is turned on by the operation pulse .phi..sub.RD, whereby the pixel MOS transistor 1 and the load capacitor element 24 are conducted. Therefore, the instant the operation MOS switch 23 is turned on, the load capacitor element 24 starts accumulating a signal charge. If the operation MOS switch 23 is turned off after the signal voltage has been stabilized sufficiently, a signal voltage which is equivalent to a channel potential corresponding to an amount (amount of holes) of signal charges accumulated in the pixel MOS transistor 1 is held in the load capacitor element 24.
The signal voltage held in the load capacitor element 24 is flowed to the horizontal signal line 10 when the horizontal MOS switches 9 are sequentially turned on by the horizontal scanning signals (i.e., horizontal scanning pulses) .phi.H (.phi.H.sub.1. . . , .phi.H.sub.n, .phi.H.sub.n+1, . . .) from the horizontal scanning circuit 8 during the horizontal scanning period. The flowed signal charge is output to the output side as a signal voltage due to a voltage drop of the output resistor 26.
After the read operation is finished, the reset MOS switch 25 is turned on on application of the reset pulse .phi..sub.RST with the result that old signal charges (holes) that had been accumulated in the load capacitor element 24 are reset, i.e., the load capacitor element 24 is reset to a predetermined voltage (e.g., ground voltage).
According to this amplifying type solid-state imaging device 28, when the signal charge is held in the load capacitor element 24, substantially no current is flowed to the vertical signal line 5. Therefore, the pixel MOS transistor 1 can substantially be prevented from being affected considerably by resistance of the vertical signal line 5 substantially and a uniform sensitivity can be obtained.
Since the electric charge is held in the load capacitor element 24, a fluctuation of signal voltage can be avoided substantially unlike the load MOS transistor 6 so that a vertical stripe-shaped fixed pattern noise (FPN) is difficult to occur.
Since the potential of the pixel MOS transistor 1 becomes a potential held in the load capacitor element 24 as it is, it is possible to increase sensitivity as compared with the case that the pixel MOS transistor 1 is driven in the stationary state, i.e., under the condition that a constant current is flowed to the channel.
Further, since the constant current is not flowed to the pixel MOS transistor 1, it is possible to reduce a power consumption.
However, in the output system shown by the amplifying type solid-state imaging device 28, i.e., in the output system in which the signal charge that was flowed to the horizontal signal line 10 is output as the signal voltage due to a voltage drop of the output resistor 26, the output signal voltage is small and output in the form of pulse-shaped signal voltage. As a result, a switching noise of the horizontal MOS switch 9 is large and an S/N (signal-to-noise ratio) is deteriorated. FIG. 3 shows an output waveform used to explain the above-mentioned disadvantage and the output pulses supplied from the horizontal scanning circuit 8, i.e., the horizontal scanning pulses .phi.H.
As shown in FIG. 3, a dotted line portion 15 in the output waveform depicts signal zero level. When this output waveform is added with a signal component, it becomes a solid-line output waveform 16.